Original Paper | “Resistance switching and retention behaviors in polycrystalline La-doped SrTiO3 ceramic chip devices,” Journal of Applied Physics, 104, 053712 (2008)
Sakyo Hirose, Akinori Nakayama, Hideaki Niimi, Keisuke Kageyama,Hiroshi Takagi
[The lead author received the 24th Excellent Presentation Award at the 2008 Spring Meeting of the Japan Society of Applied Physics (2008) and the Young Ceramist Award Best Presentation at the 27th International Korea-Japan Seminar on Ceramics (2009).]
It has long been known that forming grain boundary electrical potential barriers on ceramic boundaries of ZnO, (Sr,Ba)TiO3, etc., yields useful characteristics, such as remarkable voltage「nonlinearity specific to ceramics or positive resistance-temperature characteristics, and chips making use of such properties have been widely used in electronic equipment. This research focused on similarity of the degrading phenomenon of a ZnO varistor whose resistance varies due to electric stress with the colossal electroresistance effect (CER) expected to be the operational principle for the next generation nonvolatile memory. Through optimizing composition and process, our research team has been successful in obtainingelectric-field-induced resistance switching memory characteristics from SrTiO3 ceramic chips, similar to thin film ReRAM devices. The resistance changes reached as high as three digits, showing the potential for achieving the same functions as single-crystal thin films by using ceramic grain boundaries.